Improving the performance of Morton layout by array alignment and loop unrolling: reducing the price of naivety

Thiyagalingam, J., Beckmann, O. and Kelly, P.H.J. 2003. Improving the performance of Morton layout by array alignment and loop unrolling: reducing the price of naivety. in: Rauchwerger, L. (ed.) Languages and Compilers for Parallel Computing: 16th International Workshop, LCPC 2003, College Station, TX, USA, October 2-4, 2003: revised papers London, UK Springer.

Chapter titleImproving the performance of Morton layout by array alignment and loop unrolling: reducing the price of naivety
AuthorsThiyagalingam, J., Beckmann, O. and Kelly, P.H.J.
EditorsRauchwerger, L.
Abstract

Hierarchically-blocked non-linear storage layouts, such as the Morton ordering, have been proposed as a compromise between row-major and column-major for two-dimensional arrays. Morton layout offers some spatial locality whether traversed row-wise or column-wise. The goal of this paper is to make this an attractive compromise, offering close to the performance of row-major traversal of row-major layout, while avoiding the pathological behaviour of column-major traversal. We explore how spatial locality of Morton layout depends on the alignment of the arrays base address, and how unrolling has to be aligned to reduce address calculation overhead. We conclude with extensive experimental results using five common processors and a small suite of benchmark kernels.

Book titleLanguages and Compilers for Parallel Computing: 16th International Workshop, LCPC 2003, College Station, TX, USA, October 2-4, 2003: revised papers
Year2003
PublisherSpringer
Publication dates
Published2003
Place of publicationLondon, UK
SeriesLecture notes in computer science
ISBN3540211993
Digital Object Identifier (DOI)https://doi.org/10.1007/b95707
Journal citation(2958), pp. 241-257

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