|Chapter title||From BSP to a virtual von Neumann machine|
|Authors||Kalantery, N., Winter, S. and Wilson, D.R.|
|Editors||Halatsis, C., Maritsas, D., Philokyprou, G. and Theodoridis, S.|
Bulk synchronous parallel architecture incorporates a scalable and transparent communication model. The task-level synchronization mechanism of the machine, however, is not transparent to the user and can be inefficient when applied to the coordination of irregular parallelism. This paper presents a brief introduction to an alternative memory-level scheme which offers the prospect of achieving both efficient and transparent synchronization. This scheme, based on a discrete event simulation paradigm, supports sequential style of programming and, coupled with the BSP communication model, leads to the emergence of a virtual von Neumann parallel computer.
|Book title||PARLE'94 Parallel Architectures and Languages Europe: 6th International PARLE Conference Athens, Greece, July 4–8, 1994, Proceedings|
|Series||Lecture notes in computer science|
|Digital Object Identifier (DOI)||https://doi.org/10.1007/3-540-58184-7_157|
|Journal citation||(817), pp. 785-788|