|Chapter title||A low-power asynchronous VLSI FIR filter|
|Authors||Bartlett, V.A. and Grass, E.|
An asynchronous FIR filter, based on a Single Bit-Plane architecture with a data-dependent, dynamic-logic implementation, is presented. Its energy consumption and sample computation delay are shown to correlate approximately linearly with the total number of ones in its
coeflcient-set. The proposed architecture has the property that coefficients in a Sign-Magnitude representation can be handled at negligible overhead which, for typical filter
coefficient-sets, is shown to offer significant benefits to both energy consumption and throughput.
Transistor level simulations show energy consumption to be lower than in previously reported designs.
|Book title||19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA|
|Place of publication||Las Alamitos, USA|
|Digital Object Identifier (DOI)||https://doi.org/10.1109/ARVLSI.2001.915548|