A low-power asynchronous VLSI FIR filter

Bartlett, V.A. and Grass, E. 2001. A low-power asynchronous VLSI FIR filter. in: 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA Las Alamitos, USA IEEE . pp. 16-28

Chapter titleA low-power asynchronous VLSI FIR filter
AuthorsBartlett, V.A. and Grass, E.
Abstract

An asynchronous FIR filter, based on a Single Bit-Plane architecture with a data-dependent, dynamic-logic implementation, is presented. Its energy consumption and sample computation delay are shown to correlate approximately linearly with the total number of ones in its

coeflcient-set. The proposed architecture has the property that coefficients in a Sign-Magnitude representation can be handled at negligible overhead which, for typical filter

coefficient-sets, is shown to offer significant benefits to both energy consumption and throughput.

Transistor level simulations show energy consumption to be lower than in previously reported designs.

Book title19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA
Page range16-28
Year2001
PublisherIEEE
FileBartlett_Grass_2001_final.pdf
Publication dates
Published2001
Place of publicationLas Alamitos, USA
ISBN076951037X
Digital Object Identifier (DOI)doi:10.1109/ARVLSI.2001.915548

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Using carry-save adders in low-power multiplier blocks
Bartlett, V.A. and Dempster, A.G. 2001. Using carry-save adders in low-power multiplier blocks. in: IEEE International Symposium on Circuits and Systems (ISCAS), 2001 Las Alamitos, USA IEEE .

Permalink - https://westminsterresearch.westminster.ac.uk/item/94052/a-low-power-asynchronous-vlsi-fir-filter


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