Using carry-save adders in low-power multiplier blocks

Bartlett, V.A. and Dempster, A.G. 2001. Using carry-save adders in low-power multiplier blocks. in: IEEE International Symposium on Circuits and Systems (ISCAS), 2001 Las Alamitos, USA IEEE .

Chapter titleUsing carry-save adders in low-power multiplier blocks
AuthorsBartlett, V.A. and Dempster, A.G.
Abstract

For a simple multiplier block FIR filter design, we compare the effects on power consumption of using direct versus transposed direct forms, tree versus linear structures and carry-save (CS) versus carry-ripple (CR) adders (for which multiplier block algorithms have been designed). We find that tree structures offer power savings, as expected, as does transposition in general but not always. Selective use of CS adders is shown to offer power savings provided that care is taken with their deployment. Our best result is with a direct form CWCS hybrid.

The need for new multiplier-block design algorithms is

identified.

Book titleIEEE International Symposium on Circuits and Systems (ISCAS), 2001
Year2001
PublisherIEEE
FileBartlett_Dempster_2001_final.pdf
Publication dates
Published2001
Place of publicationLas Alamitos, USA
ISBN0780366859
Digital Object Identifier (DOI)doi:10.1109/ISCAS.2001.922212
Journal citation4, pp. 222-225
Event34th IEEE International Symposium on Circuits and Systems (ISCAS)

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