A reprogrammable computing platform for JPEG 2000 and H.264 SHD video coding

Baruffa, G., Fiorucci, F., Frescura, F., Micanti, P., Verducci, L. and Villarini, B. 2010. A reprogrammable computing platform for JPEG 2000 and H.264 SHD video coding. 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia). Scottsdale, AZ 28 Oct 2010 IEEE .

TitleA reprogrammable computing platform for JPEG 2000 and H.264 SHD video coding
AuthorsBaruffa, G., Fiorucci, F., Frescura, F., Micanti, P., Verducci, L. and Villarini, B.
TypeConference paper
Abstract

In this paper, the architecture of a DSP/FPGA based hardware platform is presented, which is conceived to leverage programmable logic processing power for high definition video processing. The system is reconfigurable and scalable, since multiple boards may be parallelized to speed-up the most demanding tasks. JPEG 2000 and H.264, both at HD and Super HD (SHD) resolutions, have been simulated and their performance found on the embedded processing cores. The results show that real-time, or near real-time, encoding is viable, and the modularity of the architecture allows for parallelization and performance scalability.

Year2010
Conference8th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia)
PublisherIEEE
Publication dates
Published2010
Journal citationpp. 107-113
Book title8th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia)
ISBN9781424490844
Digital Object Identifier (DOI)doi:10.1109/ESTMED.2010.5666990
Web address (URL) of conference proceedingshttp://www.informatik.uni-trier.de/~ley/db/conf/estimedia/estimedia2010.html

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