Adiabatic Approach for Low-Power Passive Near Field Communication Systems

Maheshwari, S. 2018. Adiabatic Approach for Low-Power Passive Near Field Communication Systems. PhD thesis University of Westminster Computer Science and Engineering

TitleAdiabatic Approach for Low-Power Passive Near Field Communication Systems
TypePhD thesis
AuthorsMaheshwari, S.
Abstract

This thesis tackles the need of ultra-low power electronics in the power limited passive Near Field Communication (NFC) systems. One of the techniques that has proven the potential of delivering low power operation is the Adiabatic Logic Technique. However, the low power benefits of the adiabatic circuits come with the challenges due to the absence of single opinion on the most energy efficient adiabatic logic family which constitute appropriate trade-offs between computation time, area and complexity based on the circuit and the power-clocking schemes. Therefore, five energy efficient adiabatic logic families working in single-phase, 2-phase and 4-phase power-clocking schemes were chosen.
Since flip-flops are the basic building blocks of any sequential circuit and the existing flip-flops are MUX-based (having more transistors) design, therefore a novel single-phase, 2-phase and 4-phase reset based flip-flops were proposed. The performance of the multi-phase adiabatic families was evaluated and compared based on the design examples such as 2-bit ring counter, 3-bit Up-Down counter and 16-bit Cyclic Redundancy Check (CRC) circuit (benchmark circuit) based on ISO 14443-3A standard. Several trade-offs, design rules, and an appropriate range for the supply voltage scaling for multi-phase adiabatic logic are proposed.
Furthermore, based on the NFC standard (ISO 14443-3A), data is frequently encoded using Manchester coding technique before transmitting it to the reader. Therefore, if Manchester encoding can be implemented using adiabatic logic technique, energy benefits are expected. However, adiabatic implementation of Manchester encoding presents a challenge. Therefore, a novel method for implementing Manchester encoding using adiabatic logic is proposed overcoming the challenges arising due to the AC power-clock.
Other challenges that come with the dynamic nature of the adiabatic gates and the complexity of the 4-phase power-clocking scheme is in synchronizing the power-clock v

phases and the time spent in designing, validation and debugging of errors. This requires a specific modelling approach to describe the adiabatic logic behaviour at the higher level of abstraction. However, describing adiabatic logic behaviour using Hardware Description Languages (HDLs) is a challenging problem due to the requirement of modelling the AC power-clock and the dual-rail inputs and outputs. Therefore, a VHDL-based modelling approach for the 4-phase adiabatic logic technique is developed for functional simulation, precise timing analysis and as an improvement over the previously described approaches.

Year2018
FileFinal_sachin_Thesis.pdf
Publication dates
PublishedSep 2018

Related outputs

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach
Maheshwari, S., Bartlett, V.A. and Kale, I. 2019. Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach. Integration, the VLSI Journal. 67, pp. 144-154. doi:10.1016/j.vlsi.2019.01.007

VHDL-based Modelling Approach for the Digital Simulation of 4-phase Adiabatic Logic Design
Maheshwari, S., Bartlett, V. and Kale, I. 2018. VHDL-based Modelling Approach for the Digital Simulation of 4-phase Adiabatic Logic Design . 28th International Symposium on Power and Timing Modeling, Optimization and Simulation. Costa Brava, Spain 02 - 04 Jul 2018 IEEE . doi:10.1109/PATMOS.2018.8464140

Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication
Maheshwari, S., Bartlett, V. and Kale, I. 2018. Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication. Integration, the VLSI Journal. 62, pp. 341-352. doi:10.1016/j.vlsi.2018.04.002

Adiabatic Flip-Flops and Sequential Circuit Design using Novel Resettable Adiabatic Buffers
Maheshwari, S., Bartlett, V. and Kale, I. 2017. Adiabatic Flip-Flops and Sequential Circuit Design using Novel Resettable Adiabatic Buffers. 23rd European Conference on Circuit Theory and Design. Catania, Italy 04 - 06 Sep 2017 IEEE . doi:10.1109/ECCTD.2017.8093257

4-phase resettable quasi-adiabatic flip-flops and sequential circuit design
Maheshwari, S., Bartlett, V. and Kale, I. 2016. 4-phase resettable quasi-adiabatic flip-flops and sequential circuit design. 12th International Conference on PhD Research in Microelectronics and Electronics. Portugal, Lisbon 27 - 30 Jun 2016 IEEE . doi:10.1109/PRIME.2016.7519498

Permalink - https://westminsterresearch.westminster.ac.uk/item/qv6w1/adiabatic-approach-for-low-power-passive-near-field-communication-systems


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