Title | Adiabatic Flip-Flops and Sequential Circuit Design using Novel Resettable Adiabatic Buffers |
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Authors | Maheshwari, S., Bartlett, V. and Kale, I. |
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Type | Conference paper |
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Abstract | We propose novel resettable adiabatic buffers for five adiabatic logic families namely; Efficient Adiabatic Charge Recovery Logic (EACRL), Improved Efficient Charge Recovery Logic (IECRL), Positive Feedback Adiabatic Logic (PFAL), Complementary Pass-transistor Adiabatic Logic (CPAL) and Clocked Adiabatic Logic (CAL). We present the design of resettable flip-flops using the proposed buffers. The proposed flip-flops alleviate the problem of increased energy and area consumption incurred by the existing mux-based resettable flip-flops. We then design the 3-bit up-down counters and extended our comparison beyond energy dissipation using the above five adiabatic logic families. PFAL based sequential circuit designs gives the best performance trade-offs in terms of complexity, energy, speed and area compared to the other adiabatic designs. |
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Keywords | adiabatic logic; energy consumption; flip-flop; performance; power-clocking scheme. |
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Year | 2017 |
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Conference | 23rd European Conference on Circuit Theory and Design |
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Publisher | IEEE |
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Accepted author manuscript | |
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Publication dates |
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Published | 02 Nov 2017 |
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ISSN | 2474-9672 |
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Book title | Proceedings of the 23rd European Conference on Circuit Theory and Design, 4-6 September 2017, Catania, Italy |
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ISBN | 9781538639740 |
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Digital Object Identifier (DOI) | https://doi.org/10.1109/ECCTD.2017.8093257 |
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Web address (URL) | http://ieeexplore.ieee.org/document/8093257/ |
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