The delta-sigma modulator (DSM) is an essential block for a Fractional-N (FN) frequency synthesizers and is used for generating the fractional part of the division ratio. Digital DSMs (DDSM) with rational input and rational initial conditions can be thought as Finite State Machines (FSM) and they always produce finite length sequences in accordance with the applied input. To provide smooth quantization noise power distribution (tone free) and to get rid of structured tones, the modulator should complete its cycle and return to initial starting state. This method is called maintaining controllable sequence length. In this paper, the practicality of this method will be investigated for DDSMs composed of up to 5th order MASH 1-1-1-1-1 structures by considering lock time requirements of the synthesizers designed for wireless transceiver applications such as GSM900, DCS-1800, UMTS(WCDMA),WLAN, ZigBee and Bluetooth.