Resettable adiabatic flip-flops are essential in the design of adiabatic counters, thus, a comprehensive study for IECRL, PFAL and EACRL 4-phase quasi-adiabatic logic families have been done in this paper. In addition, a new resettable quasi-adiabatic flip-flop circuit is proposed for each of them. Using the non-resettable and the proposed resettable adiabatic flip-flops, a practical sequential circuit comprising of a 2-bit twisted ring counter is designed and the energy consumption, for four distinct states, at different ramping times is measured. The simulation results show that the energy consumption of the resettable counter is comparable with its non-resettable counterparts. Moreover, amongst the adiabatic logic used, the PFAL based implementation of both the non-resettable and the resettable counters exhibits the least energy consumption at all ramping times.