| Chapter title | Continuous time delta sigma modulators with reduced clock jitter sensitivity |
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| Authors | Zare-Hoseini, H. and Kale, I. |
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| Abstract | In this paper, a technique and method is presented to suppress the effect of clock-jitter in continuous-time delta-sigma modulators with switched-current (current-steering) digital to analogue converters. A behavioural, transistor-level and noise analysis are presented followed by circuit-level simulations. The proposed approach which is a switched-current type of digital to analogue conversion is fully compatible with CMOS processes and multi-bit operations which are widely used in high speed applications. Moreover, having a pulse-shaped output signal does not introduce extra demands on the modulator and hence does not increase the modulator's power consumption. A third-order continuous-time /spl Delta//spl Sigma/ modulator with the proposed digital-to-analogue converter in its feedback was used for circuit-level simulations. Results proved the robustness of the technique in suppressing the clock-jitter effects. |
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| Keywords | CMOS integrated circuits, circuit simulation, clocks, continuous time systems, delta-sigma modulation, jitter switched current circuits, CMOS process, behavioural analysis, circuit-level simulations, clock jitter sensitivity, continuous time modulators, current-steering digital to analogue converters, delta sigma modulators noise analysis, switched-current digital to analogue converters, transistor-level |
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| Book title | 2006 IEEE International Symposium on Circuits and Systems. ISCAS 2006. Proceedings. |
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| Page range | 5371-5374 |
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| Year | 2006 |
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| Publisher | IEEE |
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| Publication dates |
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| Published | 2006 |
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| Place of publication | Los Alamitos, USA |
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| ISBN | 0780393902 |
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| Digital Object Identifier (DOI) | https://doi.org/10.1109/ISCAS.2006.1693847 |
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