Title | A 28mW 320MHz 3rd–Order Continuous-Time Time-Interleaved Delta-Sigma Modulator with 10MHz Bandwidth and 12 Bits of Resolution |
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Authors | Talebzadeh, J. and Kale, I. |
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Type | Conference paper |
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Abstract | this paper presents a 3rd-order two-path Continuous-Time Time-Interleaved (CTTI) delta-sigma modulator which is implemented in standard 90nm CMOS technology. The architecture uses a novel method to solve the delayless feedback path issue arising from the sharing of integrators between paths. The clock frequency of the modulator is 320MHz but integrators, quantizers and DACs operate at 160MHz. The modulator achieves a dynamic range of 12 bits over a bandwidth of 10MHz and dissipates only 28mW of power from a 1.8-V supply. |
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Keywords | time-interleaved; ΔΣ modulator; signal-to-noise ratio; |
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Year | 2017 |
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Conference | 7th International Conference on Circuits, System and Simulation (ICCSS 2017) |
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Publisher | IEEE |
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Accepted author manuscript | |
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Publication dates |
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Published | 31 Aug 2017 |
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ISBN | 9781538603925 |
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Digital Object Identifier (DOI) | https://doi.org/10.1109/CIRSYSSIM.2017.8023207 |
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