Chapter title | A high-speed, low-power interleaved trace-back memory for Viterbi decoder |
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Authors | Israsena, P. and Kale, I. |
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Abstract | This paper presents a high-speed, low-power trace-back memory structure for a Viterbi decoder. The new memory is based on an array of registers connected with trace-back signals that decode the output bits on the fly. The trace-back memory is internally interleaved such that high-speed characteristic is achieved while low-power consumption is maintained. The structure is used together with appropriate clock and power-aware control signals. The design is 100% portable and is suitable for a SoftIP approach. Based on the AMS 0.35 /spl mu/m CMOS implementation the trace-back memory is estimated to consume energy of 232 pJ, which is 53.6% less than a conventional RAM based design, with a maximum throughput of 1.1 Gbps. |
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Keywords | CMOS memory circuits, Viterbi decoding, interleaved storage, low-power electronics, 0.35 micron, 1.1 Gbit/s 232 pJ, AMS CMOS, SoftIP approach, Viterbi decoder, clock signal, high-speed characteristic, low-power consumption, power-aware control signals, registers array, trace-back memory |
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Book title | 2006 IEEE International Symposium on Circuits and Systems. ISCAS 2006. Proceedings. |
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Page range | 2801-2804 |
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Year | 2006 |
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Publisher | IEEE |
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Publication dates |
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Published | 2006 |
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Place of publication | Los Alamitos, USA |
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ISBN | 0780393902 |
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Digital Object Identifier (DOI) | https://doi.org/10.1109/ISCAS.2006.1693206 |
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