|Chapter title||Verification and FPGA circuits of a block-2 fast path-based predictor|
|Authors||Cadenas, O. and Megson, G.M.|
This paper formally derives a new path-based neural branch prediction algorithm (FPP) into blocks of size two for a lower hardware solution while maintaining similar input-output characteristic to the algorithm. The blocked solution, here referred to as B2P algorithm, is obtained using graph theory and retiming methods. Verification approaches were exercised to show that prediction performances obtained from the FPP and B2P algorithms differ within one misprediction per thousand instructions using a known framework for branch prediction evaluation. For a chosen FPGA device, circuits generated from the B2P algorithm showed average area savings of over 25% against circuits for the FPP algorithm with similar time performances thus making the proposed blocked predictor superior from a practical viewpoint.
|Keywords||Field programmable gate arrays, graph theory, instruction sets, program compilers, B2P algorithm, FPGA circuits, FPP algorithm, block-2 fast path-based neural branch prediction algorithm, graph theory, retiming methods|
|Book title||International Conference on Field Programmable Logic and Applications, Madrid, Spain, 28-30 Aug. 2006. FPL '06.|
|Digital Object Identifier (DOI)||https://doi.org/10.1109/FPL.2006.311216|