Chapter title | A clocking technique with power savings in virtex-based pipelined designs |
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Authors | Cadenas, O. and Megson, G.M. |
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Editors | Glesner, M., Zipf, P. and Renovell, M. |
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Abstract | This paper presents the evaluation in power consumption of a clocking technique for pipelined designs. The technique shows a dynamic power consumption saving of around 30% over a conventional global clocking mechanism. The results were obtained from a series of experiments of a systolic circuit implemented in Virtex-II devices. The conversion from a global-clocked pipelined design to the proposed technique is straightforward, preserving the original datapath design. The savings can be used immediately either as a power reduction benefit or to increase the frequency of operation of a design for the same power consumption. |
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Book title | Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream: 12th International Conference, FPL 2002 Montpellier, France, September 2–4, 2002: proceedings |
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Year | 2002 |
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Publisher | Springer |
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Publication dates |
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Published | 2002 |
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Place of publication | Berlin |
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Series | Lecture notes in computer science |
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ISBN | 9783540441083 |
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Digital Object Identifier (DOI) | https://doi.org/10.1007/3-540-46117-5_34 |
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Journal citation | (2438), pp. 117-151 |
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