|Chapter title|| Parallel pipelined histogram architecture via C-slow retiming|
|Authors||Cadenas, J.O., Sherratt, R.S., Huerta, P., Kao, W.C. and Megson, G.M.|
A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors of 8-bit data buses which are common in consumer digital cameras. Arrays using the new proposed cells are obtained via C-slow retiming techniques and can be clocked at a 65% faster frequency than previous arrays. This achieves over 80% of the performance of two-pixel per clock cycle parallel pipelined arrays.
|Book title||2013 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, 11-14 Jan. 2013|
|Digital Object Identifier (DOI)||https://doi.org/10.1109/ICCE.2013.6486871|