Accelerating JPEG compression with a dynamically reconfigurable FPGA systolic array
Cadenas, O., Megson, G.M. and Plaks, T.P. 2000. Accelerating JPEG compression with a dynamically reconfigurable FPGA systolic array. International Conference on Parallel and Distibuted Processing Techniques and Applications, vol VI. Las Vegas, USA 26 - 29 June 2000 pp. 3023-3026