|Chapter title||A new organization for a perceptron-based branch predictor and its FPGA implementation|
|Authors||Cadenas, O., Megson, G.M. and Jones, D.J.|
|Editors||Smailagic, A. and Ranganathan, N.|
An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.
|Keywords||Field programmable gate arrays, multilayer perceptrons predictor-corrector methods, FPGA, neural-based predictor computation, perceptron-based branch predictor, pipelined processors|
|Book title||IEEE Computer Society annual symposium on VLSI: new frontiers in VLSI design|
|Place of publication||Los Alamitos, USA|
|Digital Object Identifier (DOI)||https://doi.org/10.1109/ISVLSI.2005.11|