Chapter title | A new organization for a perceptron-based branch predictor and its FPGA implementation |
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Authors | Cadenas, O., Megson, G.M. and Jones, D.J. |
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Editors | Smailagic, A. and Ranganathan, N. |
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Abstract | An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget. |
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Keywords | Field programmable gate arrays, multilayer perceptrons predictor-corrector methods, FPGA, neural-based predictor computation, perceptron-based branch predictor, pipelined processors |
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Book title | IEEE Computer Society annual symposium on VLSI: new frontiers in VLSI design |
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Page range | 305-306 |
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Year | 2005 |
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Publisher | IEEE |
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Publication dates |
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Published | 2005 |
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Place of publication | Los Alamitos, USA |
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ISBN | 076952365X |
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Digital Object Identifier (DOI) | https://doi.org/10.1109/ISVLSI.2005.11 |
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