The impact of transistor aging on the reliability of level shifters in nano-scale CMOS technology : WestminsterResearch

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Title	The impact of transistor aging on the reliability of level shifters in nano-scale CMOS technology
Authors	Halak, B., Tenentes, V, and Rossi, D.
Abstract	On-chip level shifters are the interface between parts of an Integrated Circuit (IC) that operate in different voltage levels. For this reason, they are indispensable blocks in Multi-Vdd System-on-Chips (SoCs). In this paper, we present a comprehensive analysis of the effects of Bias Temperature Instability (BTI) aging on the delay and the power consumption of level shifters. We evaluate the standard High-to-Low/Low-to-High level shifters, as well as several recently proposed level-shifter designs, implemented using a 32 nm CMOS technology. Through SPICE simulations, we demonstrate that the delay degradation due to BTI aging varies for each level shifter design: it is 83.3% on average and it exceeds 200% after 5 years of operation for the standard Low-to-High and the NDLSs level shifters, which is 10 × higher than the BTI-induced delay degradation of standard CMOS logic cells. Similarly, we show that the examined designs can suffer from an average 38.2% additional power consumption after 5 years of operation that, however, reaches 180% for the standard level-shifter and exceeds 163% for the NDLSs design. The high susceptibility of these designs to BTI is attributed to their differential signaling structure, combined with the very low supply voltage. Moreover, we show that recently proposed level-up shifter design employing a voltage step-down technique are m
Journal	Microelectronics Reliability
Journal citation	57 (December), pp. 74-81
ISSN	0026-2714
Year	2016
Publisher	Elsevier
Accepted author manuscript	Microelect_Rel_Accepted_version.pdf
Digital Object Identifier (DOI)	https://doi.org/10.1016/j.microrel.2016.10.018
Published online	09 Nov 2016
Published	09 Nov 2016
Published in print	Dec 2016
License	CC BY-NC-ND 4.0

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The impact of transistor aging on the reliability of level shifters in nano-scale CMOS technology

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