The impact of transistor aging on the reliability of level shifters in nano-scale CMOS technology

Halak, B., Tenentes, V, and Rossi, D. 2016. The impact of transistor aging on the reliability of level shifters in nano-scale CMOS technology. Microelectronics Reliability. 57 (December), pp. 74-81. https://doi.org/10.1016/j.microrel.2016.10.018

TitleThe impact of transistor aging on the reliability of level shifters in nano-scale CMOS technology
AuthorsHalak, B., Tenentes, V, and Rossi, D.
Abstract

On-chip level shifters are the interface between parts of an Integrated Circuit (IC) that operate in different voltage levels. For this reason, they are indispensable blocks in Multi-Vdd System-on-Chips (SoCs). In this paper, we present a comprehensive analysis of the effects of Bias Temperature Instability (BTI) aging on the delay and the power consumption of level shifters. We evaluate the standard High-to-Low/Low-to-High level shifters, as well as several recently proposed level-shifter designs, implemented using a 32 nm CMOS technology. Through SPICE simulations, we demonstrate that the delay degradation due to BTI aging varies for each level shifter design: it is 83.3% on average and it exceeds 200% after 5 years of operation for the standard Low-to-High and the NDLSs level shifters, which is 10 × higher than the BTI-induced delay degradation of standard CMOS logic cells. Similarly, we show that the examined designs can suffer from an average 38.2% additional power consumption after 5 years of operation that, however, reaches 180% for the standard level-shifter and exceeds 163% for the NDLSs design. The high susceptibility of these designs to BTI is attributed to their differential signaling structure, combined with the very low supply voltage. Moreover, we show that recently proposed level-up shifter design employing a voltage step-down technique are m

JournalMicroelectronics Reliability
Journal citation57 (December), pp. 74-81
ISSN0026-2714
Year2016
PublisherElsevier
Accepted author manuscript
Digital Object Identifier (DOI)https://doi.org/10.1016/j.microrel.2016.10.018
Publication dates
Published online09 Nov 2016
Published09 Nov 2016
Published in printDec 2016
LicenseCC BY-NC-ND 4.0

Related outputs

Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs
Tenentes, V., Rossi, D., Khursheed, S., Al-Hashimi, B.M. and Chakrabarty, K. 2018. Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 37 (4), pp. 883-895. https://doi.org/10.1109/TCAD.2017.2729462

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories
Rossi, D., Tenentes, V., Reddy, S.M., Al-Hashimi, B.M. and Brown, A. 2018. Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 37 (7), pp. 1345-1357. https://doi.org/10.1109/TCAD.2017.2729399

Susceptible Workload Evaluation and Protection using Selective Fault Tolerance
Gutierrez, M.D., Tenentes, V., Rossi, D. and Kazmierski, T.J. 2017. Susceptible Workload Evaluation and Protection using Selective Fault Tolerance. Journal of Electronic Testing. 33 (4), pp. 463-477. https://doi.org/10.1007/s10836-017-5668-7

Low power probabilistic online monitoring of systematic erroneous behaviour
Gutierrez, M.D., Tenentes, V., Kazmierski, T.J. and Rossi, D. 2017. Low power probabilistic online monitoring of systematic erroneous behaviour. 2017 22nd IEEE Test Symposium (ETS). Limassol, Cyprus 22 - 26 May 2017 IEEE . https://doi.org/10.1109/ETS.2017.7968239

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
Omana, M., Rossi, D., Fuzzi, F., Metra, C., Tirumurti, C. and Galivanche, R. 2017. Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25 (1), pp. 238-246. https://doi.org/10.1109/TVLSI.2016.2572606

Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure
Tenentes, V., Rossi, D., Sheng Yang, Khursheed, S., Al-Hashimi, B.M. and Gunn, S.R. 2017. Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25 (4), pp. 1397 - 1407. https://doi.org/10.1109/TVLSI.2016.2626218

Aging Benefits in Nanometer CMOS Designs
Rossi, D., Tenentes, V, Yang, S, Khursheed, S and Al-Hashimi, B.M. 2017. Aging Benefits in Nanometer CMOS Designs. IEEE Transactions on Circuits and Systems II - Express Brief. 64 (3), pp. 324-328. https://doi.org/10.1109/TCSII.2016.2561206

Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST
Omana, M., Rossi, D., Beniamino, E., Metra, C., Tirumurti, C. and Galivanche, R. 2016. Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST. IEEE Transactions on Computers. 65 (8), pp. 2484-2494. https://doi.org/10.1109/TC.2015.2490058

Impact of Aging Phenomena on Latches’ Robustness
Omana, M., Rossi, D., Edara, T and Metra, M. 2016. Impact of Aging Phenomena on Latches’ Robustness. IEEE Transactions on Nanotechnology. 15 (2), pp. 129-136. https://doi.org/10.1109/TNANO.2015.2494612

Reliable Power Gating with NBTI Aging Benefits
Rossi, D., Tenentes, V., Sheng Yang, Khursheed, S. and Al-Hashimi, B.M. 2016. Reliable Power Gating with NBTI Aging Benefits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24 (8), pp. 2735-2744. https://doi.org/10.1109/TVLSI.2016.2519385

Cryptanalysis of Simplified-AES Encrypted Communication
Vimalathithan, R., Rossi, D., Omana, M., Metra, C. and Valarmathi, M.L. 2015. Cryptanalysis of Simplified-AES Encrypted Communication. International Journal of Computer Science and Information Security. 13 (10), pp. 142-150.

Low-Cost On-Chip Clock Jitter Measurement Scheme
Omana, M., Rossi, D., Giaffreda, D., Metra, C., Mak, T.M., Rahman, A. and Tam, S. 2015. Low-Cost On-Chip Clock Jitter Measurement Scheme. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23 (3), pp. 435-443. https://doi.org/10.1109/TVLSI.2014.2312431

Modeling and Detection of Hotspot in Shaded Photovoltaic Cells
Rossi, D., Omana, M., Giaffreda, D. and Metra, C. 2015. Modeling and Detection of Hotspot in Shaded Photovoltaic Cells. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23 (6), pp. 1031-1039. https://doi.org/10.1109/TVLSI.2014.2333064

Impact of Bias Temperature Instability on Soft Error Susceptibility
Rossi, D., Omana, M., Metra, C. and Paccagnella, A. 2015. Impact of Bias Temperature Instability on Soft Error Susceptibility. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23 (4), pp. 743-751. https://doi.org/10.1109/TVLSI.2014.2320307

DFT Architecture with Power-Distribution-Network Consideration for Delay-based Power Gating Test
Tenentes, V., Khursheed, S., Rossi, D., Sheng Yang and Al-Hashimi, B.M. 2015. DFT Architecture with Power-Distribution-Network Consideration for Delay-based Power Gating Test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 34 (21), pp. 2013-2024. https://doi.org/10.1109/TCAD.2015.2446939

Clock Faults Induced Min and Max Delay Violations
Rossi, D., Omana, M., Cazeaux, J.M., Metra, C. and Mak, T.M. 2014. Clock Faults Induced Min and Max Delay Violations. Journal of Electronic Testing. 30 (1), pp. 111-123. https://doi.org/10.1007/s10836-013-5426-4

Polynomial Based Key Distribution Scheme for WPAN
Vimalathithan, R., Rossi, D., Omana, M., Metra, C. and Valarmathi, M.L. 2013. Polynomial Based Key Distribution Scheme for WPAN. Malaysian Journal of Mathematical Sciences. 7 (S), pp. 59-72.

Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder
Rossi, D., Omana, M., Garrammone, G., Metra, C., Jas, A. and Galivanche, R, 2013. Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. Journal of Electronic Testing. 29 (3), pp. 401-413. https://doi.org/10.1007/s10836-013-5355-2

Low Cost NBTI Degradation Detection and Masking Approaches
Omana, M., Rossi, D., Bosio, N. and Metra, C. 2013. Low Cost NBTI Degradation Detection and Masking Approaches. IEEE Transactions on Computers. 62 (3), pp. 496-509. https://doi.org/10.1109/TC.2011.246

Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection
Omana, M., Rossi, D., Giaffreda, D., Specchia, R., Metra, C., Marzencki, M. and Kaminska, B. 2013. Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21 (12), pp. 2286-2294. https://doi.org/10.1109/TVLSI.2012.2230036

High-Performance Robust Latches
Omana, M., Rossi, D. and Metra, M. 2010. High-Performance Robust Latches. IEEE Transactions on Computers. 59 (11), pp. 1455-1465. https://doi.org/10.1109/TC.2010.24

Accurate Linear Model for SET Critical Charge Estimation
Rossi, D., Cazeaux, J.M., Omana, M., Metra, C. and Chatterjee, A. 2009. Accurate Linear Model for SET Critical Charge Estimation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems . 17 (8), pp. 1161-1166. https://doi.org/10.1109/TVLSI.2009.2020391

Simultaneous Switching Noise: The Relation Between Bus Layout and Coding
Rossi, D., Nieuwland, A.K. and Metra, C. 2008. Simultaneous Switching Noise: The Relation Between Bus Layout and Coding. IEEE Design & Test of Computers. 25 (1), pp. 76-86. https://doi.org/10.1109/MDT.2008.25

Power Consumption of Fault Tolerant Busses
Rossi, D., Nieuwland, A.K., Van Dijk, V.E.S., Kleihorst, R.P. and Metra, C. 2008. Power Consumption of Fault Tolerant Busses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16 (5), pp. 542-553. https://doi.org/10.1109/TVLSI.2008.917535

Checkers' No-Harm Alarms and Design Approaches to Tolerate Them
Rossi, D., Omana, M. and Metra, C. 2008. Checkers' No-Harm Alarms and Design Approaches to Tolerate Them. Journal of Electronic Testing. 24 (1), pp. 93-103. https://doi.org/10.1007/s10836-007-5031-5

Won’t On-Chip Clock Calibration Guarantee Performance Boost and Product Quality ?
Metra, C., Rossi, D. and Mak, T.M. 2007. Won’t On-Chip Clock Calibration Guarantee Performance Boost and Product Quality ? IEEE Transactions on Computers . 56 (3), pp. 415-428. https://doi.org/10.1109/TC.2007.53

Modeling Crosstalk Effects in CNT Bus Architectures
Rossi, D., Cazeaux, J.M., Metra, C. and Lombardi, F. 2007. Modeling Crosstalk Effects in CNT Bus Architectures. IEEE Transactions on Nanotechnology. 6 (2), pp. 133-145. https://doi.org/10.1109/TNANO.2007.891814

Latch Susceptibility to Transient Faults and New Hardening Approach
Omana, M., Rossi, D. and Metra, C. 2007. Latch Susceptibility to Transient Faults and New Hardening Approach. IEEE Transactions on Computers. 56 (9), pp. 1255-1268. https://doi.org/10.1109/TC.2007.1070

Permalink - https://westminsterresearch.westminster.ac.uk/item/q08w2/the-impact-of-transistor-aging-on-the-reliability-of-level-shifters-in-nano-scale-cmos-technology


Share this

Usage statistics

138 total views
257 total downloads
These values cover views and downloads from WestminsterResearch and are for the period from September 2nd 2018, when this repository was created.