|Title||Low power probabilistic online monitoring of systematic erroneous behaviour|
|Authors||Gutierrez, M.D., Tenentes, V., Kazmierski, T.J. and Rossi, D.|
Electronic devices with power-constrained embedded systems are used for a variety of IoT applications, such as geo-monitoring, parking sensors and surveillance, which may tolerate few errors and may not be constrained by a strict error detection latency requirement. In this poster, we propose a novel low power online error monitoring technique that produces an alarm signal when systematic erroneous behaviour has occurred over a pre-defined time interval. A monitoring architecture monitors the signal probabilities of the logic cones concurrently to its normal operation and compares them on-chip against the signature of error-free behaviour. Results on a set of the EPFL'15 benchmarks show an average error coverage of 82.9%% of errors induced by stuck-at faults, with an average area cost of 1.2% and an error detection latency of [0.01, 3.3] milliseconds.
|Keywords||Circuit faults, Monitoring, Systematics, Radiation detectors, Benchmark testing, Logic gates|
|Conference||2017 22nd IEEE Test Symposium (ETS)|
|Accepted author manuscript||POMSE_ETS - POSTER_accepted.pdf|
|Published||07 Jul 2017|
|Digital Object Identifier (DOI)||doi:10.1109/ETS.2017.7968239|