High-Performance Robust Latches

Omana, M., Rossi, D. and Metra, M. 2010. High-Performance Robust Latches. IEEE Transactions on Computers. 59 (11), pp. 1455-1465. https://doi.org/10.1109/TC.2010.24

TitleHigh-Performance Robust Latches
AuthorsOmana, M., Rossi, D. and Metra, M.
Abstract

First, a new high-performance robust latch (referred to as HiPeR latch) is presented that is insensitive to transient faults affecting its internal and output nodes by design, independently of the size of its transistors. Then, a modified version of the HiPeR latch (referred as HiPeR-CG) is proposed that is suitable to be used together with clock gating. Both proposed latches are faster than the latches most recently presented in the literature, while providing better or comparable robustness to transient faults, at comparable or lower costs in terms of area and power, respectively. Therefore, thanks to the good trade-offs in terms of performance, robustness, and cost, our proposed latches are particularly suitable to be adopted on critical paths.

KeywordsTransient faults, soft errors, static latch, hardened latch, robust design
JournalIEEE Transactions on Computers
Journal citation59 (11), pp. 1455-1465
ISSN0018-9340
Year2010
PublisherIEEE
Accepted author manuscript
Digital Object Identifier (DOI)https://doi.org/10.1109/TC.2010.24
Publication dates
Published22 Jan 2010

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