Power Consumption of Fault Tolerant Busses

Rossi, D., Nieuwland, A.K., Van Dijk, V.E.S., Kleihorst, R.P. and Metra, C. 2008. Power Consumption of Fault Tolerant Busses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16 (5), pp. 542-553. doi:10.1109/TVLSI.2008.917535

TitlePower Consumption of Fault Tolerant Busses
AuthorsRossi, D., Nieuwland, A.K., Van Dijk, V.E.S., Kleihorst, R.P. and Metra, C.
Abstract

On-chip interconnects in very deep submicrometer technology are becoming more sensitive and prone to errors caused by power supply noise, crosstalk, delay variations and transient faults. Error-correcting codes (ECCs) can be employed in order to provide signal transmission with the necessary data integrity. In this paper, the impact of ECCs to encode the information on a very deep sub-micrometer bus on bus power consumption is analyzed. To fulfill this purpose, both the bus wires (with mutual capacitances, drivers, repeaters and receivers) and the encoding-decoding circuitry are accounted for. After a detailed analysis of power dissipation in deep submicrometer fault-tolerant busses using Hamming single ECCs, it is shown that no power saving is possible by choosing among different Hamming codes. A novel scheme, called dual rail, is then proposed. It is shown that dual rail, combined with a proper bus layout, can provide a reduction of energy consumption. In particular, it is shown how the passive elements of the bus (bottom and mutual wire capacitances), active elements of the bus (buffers) and error-correcting circuits contribute to power consumption, and how different trade-offs can be achieved. The analysis presented in this paper has been performed considering a realistic bus structure, implemented in a standard 0.13-mum CMOS technology.

JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal citation16 (5), pp. 542-553
ISSN1063-8210
Year2008
PublisherIEEE
Digital Object Identifier (DOI)doi:10.1109/TVLSI.2008.917535
Publication dates
Published2008

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