|Title||Simultaneous Switching Noise: The Relation Between Bus Layout and Coding|
|Authors||Rossi, D., Nieuwland, A.K. and Metra, C.|
As device geometries shrink and power supply voltages decrease, simultaneous switching noise has increasingly detrimental effects on IC reliability. The authors investigate the worst-case conditions for SSN generated by a single switching wire and analyze the impact of transition-reducing encoding on SSN. They show that switching-pattern and layout considerations have a significant impact on TRE performance.
|Journal||IEEE Design & Test of Computers|
|Journal citation||25 (1), pp. 76-86|
|Digital Object Identifier (DOI)||https://doi.org/10.1109/MDT.2008.25|