Aging Benefits in Nanometer CMOS Designs

Rossi, D., Tenentes, V, Yang, S, Khursheed, S and Al-Hashimi, B.M. 2017. Aging Benefits in Nanometer CMOS Designs. IEEE Transactions on Circuits and Systems II - Express Brief. 64 (3), pp. 324-328. doi:10.1109/TCSII.2016.2561206

TitleAging Benefits in Nanometer CMOS Designs
AuthorsRossi, D., Tenentes, V, Yang, S, Khursheed, S and Al-Hashimi, B.M.
Abstract

In this paper, we show that BTI aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to sub-threshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show 50% static power reduction after only 1 month of operation, which exceeds 78% in 10 years. BTI aging benefits for power consumption are also proven with experimental measurements.

KeywordsBTI aging, leakage current, static power, nanometer technology, energy-efficiency
JournalIEEE Transactions on Circuits and Systems II - Express Brief
Journal citation64 (3), pp. 324-328
ISSN1549-7747
Year2017
PublisherIEEE
Accepted author manuscriptRossi_TCAS-II-00392-2016.pdf
Digital Object Identifier (DOI)doi:10.1109/TCSII.2016.2561206
Publication dates
Published online02 May 2016
Published in printMar 2017
Published02 May 2016

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