Low-Cost On-Chip Clock Jitter Measurement Scheme

Omana, M., Rossi, D., Giaffreda, D., Metra, C., Mak, T.M., Rahman, A. and Tam, S. 2015. Low-Cost On-Chip Clock Jitter Measurement Scheme. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23 (3), pp. 435-443. https://doi.org/10.1109/TVLSI.2014.2312431

TitleLow-Cost On-Chip Clock Jitter Measurement Scheme
AuthorsOmana, M., Rossi, D., Giaffreda, D., Metra, C., Mak, T.M., Rahman, A. and Tam, S.
Abstract

In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution.

JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal citation23 (3), pp. 435-443
ISSN1063-8210
Year2015
PublisherIEEE
Accepted author manuscript
Digital Object Identifier (DOI)https://doi.org/10.1109/TVLSI.2014.2312431
Publication dates
Published online11 Apr 2014
Published in printMar 2015
Published11 Apr 2014

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