|Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs
|Tenentes, V., Rossi, D., Khursheed, S., Al-Hashimi, B.M. and Chakrabarty, K.
Manufacturing defects that do not affect the functional
operation of low power Integrated Circuits (ICs) can
nevertheless impact their power saving capability. We show that stuck-ON faults on the power switches and resistive bridges between the power networks can impair the power saving capability of power-gating designs. For quantifying the impact of such faults on the power savings of power-gating designs, we propose a diagnosis technique that targets bridges between the power networks. The proposed technique is based on the static power analysis of a power-gating design in stand-by mode and it utilizes a novel on-chip signature generation unit, which is sensitive to the voltage level between power rails, the measurements of which are processed off-line for the diagnosis of bridges that can adversely affect power savings. We explore, through SPICE simulation of the largest IWLS’05 benchmarks synthesised using a 32 nm CMOS technology, the trade-offs achieved by the proposed technique between diagnosis accuracy and area cost and we evaluate its robustness against process
variation. The proposed technique achieves a diagnosis resolution that is higher than 98.6% and 97.9% for bridges of R ≳ 10MΩ(weak bridges) and bridges of R ≲ 10MΩ
(strong bridges), respectively, and a diagnosis accuracy higher than 94.5% for all the examined defects. The area overhead is small and scalable: it is found to be 1.8% and 0.3% for designs with 27K and 157K gate equivalents, respectively.
|power gating, diagnosis, bridging faults, stuck- ON faults, fault grading
|IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|37 (4), pp. 883-895
|Accepted author manuscript
|Digital Object Identifier (DOI)
|19 Jul 2017
|19 Jul 2017
|Published in print