DFT Architecture with Power-Distribution-Network Consideration for Delay-based Power Gating Test : WestminsterResearch

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Title	DFT Architecture with Power-Distribution-Network Consideration for Delay-based Power Gating Test
Authors	Tenentes, V., Khursheed, S., Rossi, D., Sheng Yang and Al-Hashimi, B.M.
Abstract	This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-testability (DFT) logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers trade-off flexibility between test-application time and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase test quality when considering systematic variations. Through SPICE simulations, we show complete recovery of the test quality lost due to PDNs. The proposed method is robust sustaining 80.3% to 98.6% of the achieved test quality under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on test quality and offers a unified test solution for both ring and grid power gating styles.
Keywords	power gating, dft, power-distribution-network, test quality, grid style, ring style, systematic variations
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal citation	34 (21), pp. 2013-2024
ISSN	0278-0070
Year	2015
Publisher	IEEE
Accepted author manuscript	TCAD14-AC'ED-camera-ready.pdf
Digital Object Identifier (DOI)	https://doi.org/10.1109/TCAD.2015.2446939
Published online	18 Jun 2015
Published in print	Dec 2015
Published	18 Jun 2015

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DFT Architecture with Power-Distribution-Network Consideration for Delay-based Power Gating Test

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