Metra, C., Rossi, D. and Mak, T.M. 2007. Won’t On-Chip Clock Calibration Guarantee Performance Boost and Product Quality ? IEEE Transactions on Computers . 56 (3), pp. 415-428. https://doi.org/10.1109/TC.2007.53
| Title | Won’t On-Chip Clock Calibration Guarantee Performance Boost and Product Quality ? |
|---|---|
| Authors | Metra, C., Rossi, D. and Mak, T.M. |
| Abstract | In today's high performance (multi-GHz) microprocessors' design, on-chip clock calibration features are needed to compensate for electrical parameter variations as a result of manufacturing process variations. The calibration features allow performance boost after manufacturing test and maintain such performance levels during normal operation, thus preserving product quality. This strategy has been proven successful commercially. In this paper, we discuss the impact on performance and product quality of both permanent and transient faults possibly affecting these calibration circuits during manufacturing and normal operation, respectively. In particular, we consider the case of an on-chip clock calibration feature of a commercial high performance microprocessor. We show that some possible permanent faults may render the on-chip clock calibration schemes useless (in process variations' compensation), while it is impossible for common manufacturing testing to detect this incorrect behavior. This means that a faulty operating microprocessor may pass the testing phase and be put onto the market, with a consequent impact on product quality and increase in defect level. Similarly, we show that some possible transient faults occurring during the microprocessor in-field operation could defeat the purpose of on-chip clock calibration, again resulting in faulty operation of the microprocessor. This has long range implications to microprocessors' design as well, considering that process variations on die, as well as across the process, would worsen with continued scaling. Proper strategies to test these clock calibration features and to guarantee their correct operation in the field cannot be ignored. Possible design approaches to solve this problem are discussed. |
| Keywords | Reliability, testing, fault tolerance, VLSI |
| Journal | IEEE Transactions on Computers |
| Journal citation | 56 (3), pp. 415-428 |
| ISSN | 0018-9340 |
| Year | 2007 |
| Publisher | IEEE |
| Digital Object Identifier (DOI) | https://doi.org/10.1109/TC.2007.53 |
| Publication dates | |
| Published | 2007 |